The present invention relates in general to frequency synthesizers, and in particular, to a technique to compensate for tuning gain variations.
With reference to FIG. 1, an exemplary fractional-N frequency synthesizer 12 is illustrated according to one embodiment of the present invention. The synthesizer 12 includes a fractional-N phase lock loop (PLL) 14, and generates a desired frequency for the output signal, FVCO, 16, of a voltage controlled oscillator (VCO) 18. In traditional fashion, the output signal FVCO 16 is also provided to divider circuitry 20 to divide the output signal FVCO by a factor N to produce a divided VCO signal FV, which is fed to one of two inputs of a phase detector 22.
A reference signal, FREF, is divided by a factor R in divider circuitry 24 to produce a divided reference signal, Fr, which is provided to the other input of the phase detector 22. The N and R factors are selected so that the frequencies of the divided reference signal, Fr, and the divided VCO signal, FV are equal when the desired output signal, FVCO, 16, is at a desired frequency. The phase detector 22 compares the relative phases of the divided reference signal, Fr, and the divided VCO signal, FV, and provides an output relative to the difference in phase to drive a charge pump 26.
The phase detector 22 is typically an asynchronous digital logic circuit that pulses either pump up (PU) or pump down (PD) signals for the duration of time between rising edges on the reference signal, Fr, and divided VCO signal, FV. The PU and PD signals cause the charge pump 26 to source or sink current, ICP, from a low pass filter, generally referred to as the loop filter 28. The loop filter 28 is typically a passive or active RC filter, and the one or more pulses of current are integrated and stored on the loop filter""s capacitors as charge. The output voltage of the loop filter 28 is a function of this charge, and acts as the tuning control voltage VCON of the VCO 18. The N divider circuitry 20 is typically a programmable integer or fractional divider, which is used to set the output frequency of the VCO 18. The PLL 14 acts as a feedback control system to drive the phase, and therefore frequency, error of the Fr and Fv signals to zero. Since Fv=FVCO/N, where N is the divider modulus, the VCO frequency is set to FVCO=N Fr.
The behavior of the PLL 14 in terms of noise and dynamic response is determined by the loop gain of the system. The loop gain is given by:                                           G            ⁡                          (              s              )                                =                                                    I                                  CP                  ⁢                                      xe2x80x83                                                              ⁢                              K                v                            ⁢                              F                ⁡                                  (                  s                  )                                                      sN                          ,                            Eq        .                  xe2x80x83                ⁢        1            
where s is the Laplace frequency variable, ICP is the charge pump current in amperes (A), KV is the tuning gain in cycles-per-second-per-volt (Hz/V), F(s) is the loop filter transfer function, and N is the VCO divider modulus. A typical filter transfer function contains a gain set by a capacitance, or combination of capacitances, an integration function, and a lead-lag pole/zero combination to set the phase margin of the loop:                               F          ⁡                      (            s            )                          =                              1            sC                    ⁢                                                    (                                                      s                    ⁢                                          xe2x80x83                                        ⁢                                          τ                      z                                                        +                  1                                )                                            (                                                      s                    ⁢                                          xe2x80x83                                        ⁢                                          τ                      p                                                        +                  1                                )                                      .                                              Eq        .                  xe2x80x83                ⁢        2            
The unity loop gain frequency, also referred to as the loop bandwidth, is given by:                     BW        =                                                            I                CP                            ⁢                              K                v                            ⁢                              K                f                                      NC                                              Eq        .                  xe2x80x83                ⁢        3            
where the variable, Kf, is a factor that depends on the locations of the poles and zeros. Note that the loop bandwidth depends not only on the pole and zero locations, but also on the loop gain constant set by the charge pump current, ICP, the loop divider value, the filter capacitance, and the VCO tuning gain.
Modern communication systems, such as the GSM cellular telephone system, impose strict requirements on the locktime and noise performance of the transmitted signal, and on the signals used for mixing in the receiver. For example, the transmit locktime must typically be under 250 xcexcs to settle the VCO to under 100 Hz error, and the transmitted phase noise must be underxe2x80x94113 dBc/Hz at 400 kHz offset. If the loop bandwidth is too wide, the noise performance may not be met, and if the loop bandwidth is too narrow, the locktime may not be met. In addition, the phase error of the transmitted signal must remain small. For example, the phase error of the transmitted signal must be under five degrees rms in a GSM system.
The use of fractional-N synthesis enables digital modulation for phase or frequency based systems and is attractive due to reduced complexity of the transmit system relative to traditional analog modulation techniques. However, variations in loop gain, and thus bandwidth, can degrade the performance of fractional-N based transmit systems in which a fixed predistortion filter is used to compensate for the rolloff of the loop responses. Mismatch between the expected and actual loop response degrades the phase error of the transmitted signal. Simulations indicate that the loop gain must be accurate to within 15% of the expected nominal value for a 120 kHz loop bandwidth and fixed predistortion filter for less than 5 degrees rms phase error.
While the pole and zero locations, which depend on RC time constants, and the charge pump current, ICP, and loop divider variations can be compensated by methods known in the prior art, the VCO tuning gain, KV, poses a more difficult problem. The tuning gain, KV, of the VCO 18 characterizes the sensitivity of the VCO output frequency, FVCO, to changes in its tuning control voltage, VCON. The tuning gain, KV, is defined as:                               K          v                ≡                                            ⅆ                              F                VCO                                                    ⅆ                              V                c                                              .                                    Eq        .                  xe2x80x83                ⁢        4            
The tuning gain, KV, is usually not constant, and for an integrated, wide-range VCO, the tuning gain can vary as much as three to one over the desired tuning range.
Although methods of xe2x80x98flatteningxe2x80x99 the variation in the tuning gain curve have been advanced, these methods typically require more complex tuning methods employing additional circuit elements. It is desirable to avoid any additional cost or complexity in the VCO, since the material cost, noise, and power consumption constraints are usually very tight.
Thus, instead of compensating the VCO 18 directly, the loop gain of the PLL 14 can be compensated by adjusting another gain term. For example, the charge pump current may be modified to compensate for variation in the tuning gain. This requires, first, a method of measuring the tuning gain, and second, a method of applying the appropriate adjustment.
Two methods have traditionally been used to characterize the tuning gain. The first is to measure or characterize the tuning gain of the VCO once and construct a table of tuning gain versus operating frequency, such a method is described in U.S. Pat. No. 4,893,087, issued Jan. 9, 1990, which is incorporated herein by reference. The table is then mapped to an adjustment factor for the charge pump current ICP versus the VCO divider value, and is stored in a non-volatile memory. While the nominal loop gain adjustments may be known for a xe2x80x98typicalxe2x80x99 VCO 18, the accuracy of nominal adjustments is not sufficient for high performance communications systems when integrated components with large tolerances are used. Hence, this method has the drawbacks of requiring an extensive one-time measurement process on each product that runs through the factory, and of requiring a non-volatile storage means within each product, which unduly increases costs.
The second method is to indirectly measure the closed loop bandwidth, which depends to a large extent on the loop gain. This type of method typically requires a modulation source to be applied to the VCO 18, and a frequency discriminator to determine the frequency deviation of the VCO 18 while the PLL 14 is locked as noted in U.S. Pat. No. 5,079,522, issued Jan. 7, 1992, which is incorporated herein by reference. If the loop bandwidth is wider than the modulation frequency applied to the VCO 18, the frequency deviation of the VCO 18 will be lower than if the loop bandwidth is narrower than the modulation frequency. A similar method could apply modulation through the loop divider.
In either of the above cases, the allowable deviation may be very small relative to the center frequency of the VCO, requiring a very accurate frequency discriminator or counter. For example, in a GSM cellular phone, the VCO 18 may be running at 1900 MHz, and may have an allowable deviation of only 20 MHz due to tuning voltage constraints. This is a deviation of less than ten percent (10%). In a system employing GMSK modulation through a fractional-N PLL, the GSM rms phase accuracy specification requires that the loop gain must be measured and corrected to within a 15% error, as discussed above. The actual frequency measurement accuracy would need to be 0.15*0.1=0.005=1.5%. This accuracy requires a long calibration time, which may be too long to perform each time the phone switches to a new transmission frequency.
Thus, what is needed is a fast and low complexity calibration technique that provides a desired, arbitrary level of accuracy with minimal overhead in terms of device area and calibration time. The calibration should complete rapidly enough to be performed each time the frequency synthesizer is enabled. The system should also function automatically, with little or no user intervention.
The present invention provides for compensating for tuning gain variations in a phase-locked loop. Compensation is performed by a calibration system that estimates the tuning gain of the oscillator and then adjusts the charge pump current value by a ratio of the nominal tuning gain to the measured tuning gain. The tuning gain measurement is performed by measuring the change in the voltage controlled oscillator""s tuning control voltage when the phase-locked loop is locked to two different frequencies, which are separated by a fixed, predetermined amount. The two frequencies may be above or below the final output frequency of the VCO, or the second frequency may be the final frequency, in order to reduce calibration time and settling time. Use of the system in a fractional-N phase-locked loop takes advantage of the fast locking properties, afforded by the high loop bandwidth and reference frequency such that there is minimal impact to warm-up time for the entire system. The system provides accurate calibration of phase-locked loop gain and bandwidth, which is important to guarantee settling time, noise performance, and modulation accuracy.